The Nikon eReview: Intel Expert Discusses Lithography Technology and Future Trends

Presenting his view on immersion and future lithography trends at the 2009 LithoVision symposium earlier this year, Mr. Sam Sivakumar, Intel Fellow and Director of Lithography at Intel Corporation’s Technology Development Group in Oregon, announced that immersion has successfully moved into the production phase.

Mr. Sivakumar shared 32 nm node immersion defectivity and CD control data demonstrating performance comparable to dry lithography, and commented that significant learning about thermal, focus, and alignment effects (at the wafer edge in particular), have made wet-dry overlay accuracy roughly equivalent to dry-dry overlay performance.

Figure 1. 32 nm node immersion defectivity and CD control data demonstrating performance comparable to dry lithography.

Sivakumar reported that immersion lithography has been a story of steady progress with regard to tool integration, operation and stability, as well as defectivity and overlay. He summarized the status of immersion lithography as being "…well on the way to achieving yield parity with dry lithography."

Figure 2. Sivakumar reported immersion lithography is "…well on the way to achieving yield parity with dry lithography."

Looking beyond single patterning immersion applications, Sivakumar commented that ArF pitch division (PD) provides marked resolution enhancements, but noted it is at the expense of increased process complexity. Double patterning pitch division (DPPD) using LELE (litho-etch-litho-etch) or LFLE (litho-freeze-litho-etch) is one solution, but misalignment between the two exposures are a liability for pitch division, and Sivakumar highlighted that transistor parameters can be impacted by asymmetry between the source and drain regions. Spacer-based pitch division (SBPD) is another viable solution that provides edge placement advantages and is likely to require fewer masks overall, but it is difficult for random layouts. Sivakumar concluded that both of these pitch doubling methods are technically straightforward, have clear pros and cons, and will be implemented based on the specific application.

Figure 3. ArF immersion with pitch division will be used to provide the necessary process latitude beyond ~40 nm half-pitch. EUV introduction will likely be gated by technology readiness and cost of ownership relative to pitch doubling.

Transitioning then to discussion of EUV, Sivakumar reported that although significant progress has been made on numerous fronts, challenges such as tool integration, source power, resists, and mask defect inspection still exist. He highlighted insufficient (or lack of) funding across several areas, and stressed that if the technical gaps (particularly in mask defectivity and inspection) are not resolved in time, high-volume manufacturing insertion of EUV will be limited.

Sivakumar summarized his presentation stating that immersion has successfully moved into the production phase, and that ArF immersion with pitch division will be used to provide the necessary process latitude beyond ~40 nm half-pitch (hp). EUV introduction will be gated by technology readiness and cost of ownership relative to PD, and may be in time for the 26 – 30 nm hp. In closing, Sivakumar highlighted that currently no simple pitch division solution exists below ~20 nm hp and questioned how that solution, whether it's EUV or some other ArF extension, will be made affordable.