Wafer Defect Inspection and Review Advances to Address Cost and Productivity Challenges in the Fab

With the beginning economic recovery and a tentative increase in consumer demand over the past quarter, fabs are once again thinking about maximizing the productivity of their capital equipment as they ramp manufacturing. In this article we focus on the productivity of wafer defect inspection and review systems.

IC fabs want inspection and review systems to reliably and quickly recognize defect excursions, facilitate root-cause defect analysis, and effect faster, more efficient ramps. False alarms consume resources and delay manufacturing ramps, while missed defect excursions can result in millions of dollars’ worth of scrapped parts and wasted engineering time. These false positives and false negatives increase manufacturing cycle time and delay time to market.

This problem can be attacked on several fronts. Sufficient inspection sensitivity is required— measured not just by resolution of the optics or performance on artificial defect standards, but by the system’s ability to capture a wide range of defect types (shapes, sizes and materials) under varied conditions such as: film material, surface roughness, nearby patterned features, and artifacts from previous layers. As measured by these more complex and realistic means, the best overall inspection sensitivity is given by an inspection system having the ability to vary illumination wavelengths, apertures, polarizations, and signal processing algorithms. A broadband brightfield inspection system such as KLA-Tencor’s 2830 Series provides the desired flexibility and sensitivity.

When a defect inspection system is operated at high sensitivity, the potential for “nuisance” defects is elevated. Nuisance defects derive from real physical phenomena on the wafer, (a glitch in the system itself would be a ‘false’ defect) but do not affect device performance or yield. These include particles on a dummy pattern or in an isolated area of the die. Effective filtering of nuisance defects requires that they be reliably distinguished from defects of interest (DOI). Then the inspection “recipe”—the optical, mechanical and algorithm parameter settings governing the inspection—can be set up to minimize capture of nuisance defect types. Identification of defect types involves both the inspection and e-beam review systems.

Traditionally a file of defect coordinates from a high-sensitivity (“hot”) inspection is sent to the e-beam review system along with the wafer. The e-beam system visits a sample of the defect sites and the operator sorts the defects into types. The wafer is transferred back to the inspection tool, the inspection recipe is altered, and the new results are examined on the review tool. This iterative process of transferring the wafer back and forth, adjusting inspector recipe parameters and reviewing results, is declared finished when the percentages of nuisance and DOI were optimized—or more likely, when the time the fab allotted for recipe optimization is up.

A complicating issue is that the e-beam review tool may not be able to re-detect all of the defects found by the inspector. Perhaps the coordinate accuracy of either of the two systems is lacking. If the review tool compensates for insufficient coordinate accuracy by using a large field of view, it may not have sufficient resolution to re-detect the defect. Likewise, the difference between optical and e-beam physics could interfere with re-detection. For example, a defect underneath a layer transparent at inspection wavelengths will often be invisible to the e-beam tool because the electrons do not penetrate far enough into the material. In any of these cases, a defect will be classified as SEM Non-Visual (SNV) by the review tool. SNV defects often represent the largest category of the defect Pareto—the strongest “pollutant.”

Three recent advances have helped to improve the speed of inspection recipe setup and the quality of the resulting defect Pareto. First, SNV rates have been dramatically reduced in the newest e-beam review systems through a combination of advancements in resolution and coordinate accuracy. Subsurface defects can be distinguished by allowing the inspector to transmit an optical image of the defect to the SEM, for comparison with the SEM image.

Second, a capability called RICO (Review Inspector Cycle Optimization) allows the inspection recipe to be optimized on the SEM using results from a “hot” inspection scan: all inspection-recipe adjustments required to maximize DOI and reduce nuisance are made on the SEM. This new process not only markedly reduces iterations between the inspector and review tool, but also frees up capacity on the more expensive inspection system.

Figure 1. Design-aware setup, inspection, binning and review have accelerated root-cause defect analysis in the fab.

Third, a new option called XP gives an inspection system access to standard IC design layout files—the instructions that enable mask shops to pattern the mask. With access to this information, the inspection system can use knowledge of the defect’s location within the circuit to better estimate its probability of affecting device yield (Figure 1).

Both RICO and XP are available as upgrades to KLA-Tencor’s existing broadband DUV inspection systems already present in most leading-edge fabs. The ability to reduce the SNV rate is a benefit of the eDR-5210 e-beam review system, especially when used with a 28XX inspection system. These advances are designed to improve the sensitivity and productivity of inspectors and review tools, raise the information content of the defect Pareto, and accelerate identification and resolution of defect issues. Inspection innovations such as these are vital in enhancing fab productivity and yield as IC manufacturers begin to once again ramp up production.